1. Field of the Invention
The present invention relates to a method of analyzing electromagnetic interference (EMI) and an apparatus for analyzing electromagnetic interference, and more particularly to a method of performing high-speed and accurate EMI analysis on a large and high-speed driven LSI (Large Scale Integrated circuit) to analyze electromagnetic interference.
2. Description of the Related Art
The range in which an LSI is useful is expanding not only to a computer, but also to a communication device such as a portable telephone, usual housewares, a tool, and an automobile. On the other hand, there is a problem in that electromagnetic interference produced in such a product causes radio wave interference in a receiving device such as a television receiver and a radio set, or a malfunction of another system. In order to solve the problem, a countermeasure such as provisions of a filtering device or a shielding device is taken for the whole of a product. However, such a countermeasure increases the number of parts and the production cost, and is difficult to be taken on a product. From the viewpoints of these disadvantages and the like, it is strongly requested to apply noise suppression on an LSI package itself.
Under these circumstances, an LSI is positioned at a key device of each product, and is requested to be increased in scale and speed in order to ensure the competitiveness of the product. In view of a shortened product cycle, it is necessary to automatically design an LSI, and the need for employing synchronous design as conditions for introducing a current design automating technique is growing. In the case of a large and high-speed driven LSI in which all circuits operate in synchronization with a reference clock, an instantaneous current of a very high level flows to cause increased electromagnetic interference.
The invention relates to a method of analyzing EMI in which EMI evaluation that is essential to reduce electromagnetic interference is enabled while maintaining the large scale and the high-speed operation of an LSI.
Noise which is generated by an LSI to damage other systems is roughly classified into radiative noise and conductive noise. Radiative noise which is generated directly from an LSI includes noise which is radiated from internal lines of the LSI. However, internal lines do not constitute a large antenna. Since the operating frequency of an LSI is expected to be raised, noise which is radiated directly from an LSI may cause a problem in the future. At present, however, the level of radiative noise from the inside of an LSI is not so high to cause a problem.
By contrast, conductive noise affects other devices on a printed circuit board through direct connecting means such as wires in an LSI, a lead frame, a package, and lines on the printed circuit board, and noise is radiated by using the connection paths as an emission source, i.e., an antenna. This antenna configured by the connection paths is very larger than lines in the LSI, and functions as a dominant factor from the viewpoint of electromagnetic interference.
With respect to conductive noise from an LSI, a power source and a signal function as paths. In a surrounding electromagnetic field, however, noise which is caused by changes of a current of a power source and radiated by using power source lines as an antenna seems to be dominant.
In a signal, ringing and overshoot which are generated at a change of the signal may cause a problem. However, it is often that a phenomenon that variation of the power source level in an LSI is transmitted as a current waveform becomes a problem. It seems that also noise which is transmitted through either of the power source path or a signal path and then radiated closely correlates with a change of the power source current.
In addition to the power source, furthermore, also a package often becomes a problem.
Recently, EMI noise in an LSI is seriously problematic. Therefore, IEC (International Electrotechnical Commission) intends to standardize a method of measuring EMI noise in an LSI, and analyzing methods such as the magnetic probe method and the VDE method have been proposed.
When a measuring method is standardized, LSI vendors can stay on the equal footing to push EMI noise performances of their respective LSIs to the customers. The customers can perform absolute comparison from the viewpoint of EMI noise, on LSIs. It seems that, when such a standard measuring method is widely used, an EMI noise standard for an LSI will be naturally established.
Conventionally, a measurement system (a measuring apparatus and a printed circuit board which is used in measurement) is not considered. In a phase of developing an LSI, therefore, it is impossible to judge whether the standard is satisfied or not.
The power source current of a CMOS circuit will be described by using a simple inverter circuit. When an input voltage of an inverter circuit is changed, load capacitance charging and discharging currents which mainly constitute the power source current of the CMOS circuit flows. Furthermore, a through current additionally flows. In a design of such a CMOS circuit, synchronization is conducted because of constraints of using an automatic design tool. Because of the synchronization, circuits of the whole LSI simultaneously operate, and hence a peak current is generated in the power source in synchronization with a reference clock. In order to increase the speed or to shorten the period, transistors are designed so as to be large, thereby enabling charging and discharging operations to be conducted in a short time period. As a result, the peak current is increased. Of course, the power source current of the whole LSI is increased also by enlarging the LSI. In this way, the peak current of the power source is increased, and the power source current is steeply changed. This steep change increases harmonic components, thereby causing electromagnetic interference to be enhanced.
An accurate simulation of a change of the power source current which would be the principal factor of electromagnetic interference seems to be effective in evaluation of electromagnetic interference in an LSI.
Conventionally, a current simulation technique in which a current analysis is conducted at the transistor level as described below is used.
FIG. 46 is a chart showing a process flow of a conventional EMI analyzing method which uses a current simulation technique at the transistor level. This method is configured so that a layout parameter extraction (hereinafter, abbreviated to LPE) process is performed on the basis of layout information of an LSI which is to be analyzed, and steps of a circuit simulation, a current source modeling process, a power source line LPE process, a transient analysis simulation, and an FFT process are performed on a switch level netlist.
Hereinafter, the steps will be described with reference to FIG. 46. In step 4603, layout data 4601 of a semiconductor integrated circuit on which EMI analysis is to be performed, and an LPE rule 4602 in which transistor elements and various parasitic line elements (resistors, capacitors, and the like), parameter values of the elements, and output formats of extraction results are defined are input. Based on the LPE rule 4602, parameters of the elements in the layout data 4601 are calculated to generate a netlist 4604. In this step, parasitic elements of the power source (and ground) lines are not set as extraction objects.
In step 4606, the netlist 4604 which is generated in previous step 4603, and a test pattern 4605 for reproducing a desired logical operation in a circuit to be analyzed are input. In accordance with the operation states of internal circuits, load capacitance charging and discharging currents, a through current, and the like are calculated to generate current waveform information 4607 for each transistor. In the initial process of this step, it is assumed that the power source (and ground) potential is an ideal potential which is free of variation.
In step 4608, the current waveform information 4607 for each transistor which is generated in previous step 4606 is input, and each of the information is modeled into a form which is applicable in subsequent step 4612, thereby producing current source element model information 4609. Usually, a technique of modeling each functional circuit block configured by plural transistors as a current source element is employed in order also to reduce the processing load of subsequent step 4612.
Step 4610 is identical with step 4603 except that the extraction objects are parasitic elements (resistors, decoupling capacitors, and the like) of the power source and ground lines in place of transistor elements and various parasitic line elements on which EMI analysis is to be performed. Therefore, description of the step is omitted. In this step, a power source (and ground) line netlist 4611 is generated.
In step 4612, the current source element model information 4609 which is generated in previous step 4608, the power source (and ground) line netlist 4611 which is generated in previous step 4610, and an impedance (resistance, capacitance, and inductance) 4616 of wires and a lead frame are input. A power source voltage drop result 4617 in which power source voltage variation of the circuit to be analyzed is calculated is generated by analysis using a transient analysis simulator which is typified by SPICE.
Thereafter, the process of step 4606 is again performed. In this case, by contrast to the initial process of step 4606 in which it is assumed that the power source (and ground) potential is an ideal potential which is free of variation, the power source voltage drop result 4617 which is generated in previous step 4612 is input, and the current waveform information 4607 for each transistor in which the power source voltage variation is considered is again generated. Similarly, steps 4608 and 4612 are again performed.
When the loop process of steps 4606, 4608, and 4612 is repeated plural times, a current waveform result 4613 in which the power source voltage variation is accurately reproduced is generated. In step 4614, the current waveform result 4613 which is generated in previous step 4612 is input, and fast Fourier transform (hereinafter, abbreviated to FFT) is applied, thereby enabling frequency spectrum analysis to be performed. Then, it is possible to obtain an EMI analysis result 4615.
In the conventional art example, it is expected to attain an analysis accuracy of a certain level although the verification accuracy largely depends on matching of the LPE process 4603, the power source line LPE process 4610, and the current source modeling process 4608. In such current analysis at the transistor level, however, a transient analysis simulator which is typified by SPICE is used. Therefore, the scale of a circuit on which EMI analysis is to be performed is limited and the process time period is prolonged. Recently, the scale of a semiconductor integrated circuit is being enlarged, and hence it is requested to establish an EMI analyzing method in which the degree of abstraction is higher than the transistor level and analysis can be rapidly performed.
As an EMI current analyzing method the speed of which can be increased, EMI current analyzing methods at the gate level have been proposed. An example of such methods is EMI-noise analysis under an ASIC design environment which is described in pp. 16 to 21 of ISPD & 99 (EMI-NOISE ANALYSIS UNDER ASIC DESIGNS ENVIRONMENT’ ISPD & 99). In this technique, an event is obtained from a result of a gate-level simulation using test vectors, a current waveform is inferred, and frequency analysis is performed by FFT. Specifically, as shown in FIG. 47, a logical simulation 4703 is performed on the basis of Verilog Netlist 4701 and test vectors 4702, and a waveform inferring step 4705 is performed on the basis of event data 4704 calculated in the simulation, and waveform information 4706 at a toggling operation. An FFT process is performed on an inferred current waveform 4707 which is obtained in the waveform inferring step, to obtain frequency characteristics. In this method, the speed can be increased as compared with conventional EMI analysis at the transistor level.
In a logical simulation, usually, the power source and the ground are deemed as an ideal potential which is free of variation, and hence an influence of decoupling due to the resistance, the capacitance, and the inductance of the power source and the ground cannot be reflected in the power source current calculation. When the influence of decoupling is to considered, it is required to apply transient analysis on current values of elements which are obtained from the network of the power source and the ground including parasitic element such as the resistance, the capacitance, and the inductance, and a logical simulation. Therefore, the time period required for the process is extremely prolonged.
Because of tendency of increasing the chip scale and the number of elements, the scale of a network of power source lines is being increased, and such a prolonged process time period constitutes a serious obstacle to analysis of electromagnetic interference. In order to shorten the process time period, reduction means for the resistance and the capacitance of such power source lines has bee proposed. However, this countermeasure is restricted to a gate array in which power source lines are arranged in a lattice structure.
Even when EMI analysis is performed by applying FFT to power source current values, the designer oneself must judge FFT characteristics. According to this means, it requires a very long time period or is impossible to identify a causing place. The means has a further problem in that analysis information is insufficient for being directly reflected in correction.
Since also a package and a measurement system contain an inductance, the process time period is prolonged, thereby causing a problem which cannot be neglected in analysis of electromagnetic interference.
As described above, the conventional methods of analyzing electromagnetic interference in an LSI are not sufficient from the viewpoints that consideration of the resistance, the capacitance, and the inductance of the power source and the ground, and also the measurement system is compatible with high-speed processing, and that a result of analysis of electromagnetic interference is rapidly reflected in the design.
As described above, in the conventional art examples using a current analyzing technique at the transistor level, it is expected to attain an analysis accuracy of a certain level. However, a transient analysis simulator which is typified by SPICE is used in such current analysis at the transistor level. Therefore, the scale of a circuit to be analyzed is limited and the process time period is prolonged. Recently, the scale of a semiconductor integrated circuit is being enlarged, and hence it is requested to establish an EMI analyzing method using a current analyzing technique at the gate level in which the degree of abstraction is higher than the transistor level and analysis can be rapidly performed.
On the other hand, also a current analyzing technique at the gate level has been proposed. However, this technique has problems in that, when the power source and the ground, and also the measurement system are handled at an ideal potential which is free of variation, the decoupling effect cannot be considered, and that, when transient analysis is applied on the network of the power source and the ground including parasitic elements in order to consider decoupling, the analysis time period is prolonged.
Conventionally, the problems of a measurement system including such a measuring apparatus and a printed circuit board which is used in measurement are not considered. Consequently, there arises a problem in that, in a phase of developing an LSI, it is impossible to judge whether the above-mentioned standard is satisfied or not.
Even when EMI analysis is performed, a circuit in which the main cause exists cannot be known, thereby causing a further problem in that it is impossible to know which circuit is to be corrected in order to improve EMI.
In order to provide a method and an apparatus for analyzing electromagnetic interference in which, while high-speed analysis is performed, an influence of decoupling due to the resistance, the capacitance, and the inductance of the power source and the ground is reflected in a power source current calculation, whereby electromagnetic interference of an LSI can be evaluated in a simulation within a realistic time period, the inventors have proposed a method of analyzing electromagnetic interference which includes steps of; allocating a discrete width of FFT analysis for each frequency band and performing a modeling process; and applying a fast Fourier transform process on current change information which is calculated by the modeling step (Japanese patent application No. 2000-63783).
Also a method has been proposed in which an inferred current waveform of each logical change in a digital simulation is set to a triangular wave the base of which is expressed by a function of a transition time, thereby enabling high-speed processing (Japanese patent application No. 11-196190).
In this method, an influence of the decoupling capacitance on an FFT result cannot be expressed, and, in order to express the influence, the base of the triangle must be widened. When the base is widened, however, such an influence cannot be correctly expressed, thereby causing a problem in that the widening cannot attain an effect.
Furthermore, a mixed mode simulation method in which an analog portion is analyzed in synchronization with a digital simulation has been proposed (Japanese patent application No. 4-54215).
In the method, reflection to the analog portion is considered, but an influence on a power source netlist is not considered. Therefore, the method has a problem in that the accuracy is low from the viewpoint of EMI noise analysis.
Since a synchronization calculation is performed, a current must be calculated after a logical change of a digital portion although a current change due to the logical change is originally generated before the logical change. Therefore, the method has another problem in that it is impossible to correctly reflect the power source current.
As described above, also EMI which is caused by a package is as high as an unnegligible level. Consequently, the method has a further problem in that an obtained value is different from a measured value unless EMI due to a measurement system is considered in addition to circuit information of an LSI chip.